1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, in particular to a halo ion implantation method for a semiconductor device which enhances data maintenance characteristics by not allowing sources/drains of a cell transitor of a Dynamic Random Access Memory(hereinafter DRAM) to be exposed to the halo ion implantation.
2. Description of the Background Art
A halo ion implantation means implanting conductive impurity ions identical with a semiconductor substrate into the semiconductor substrate along the inside sidewalls of sources/drains of a transistor in order to prevent a short channel effect. As a result, the impurity concentration of the semiconductor substrate near the inside sidewalls of the sources/drains becomes higher than that of the semiconductor substrate in other part.
Referring to FIGS. 1a through 1c, a conventional halo ion implantation method will be explained as follows.
A shown in FIG. 1a, a gate oxide film 101 and a gate electrode 102 are formed on a first conductive type(e.g. p-type) semiconductor substrate 100.
Next, using the gate electrode 102 as a mask, a second conductive type(e.g. n-type) impurity ions are implanted into the semiconductor substrate and heat-treated, thus forming an impurity layer 103 with a relatively shallow junction depth as compared with sources/drains which will be explained in the following process step. The second conductive type impurity ions are opposite to the first conductive type impurity ions.
Next, as shown in FIG. 1b, the impurity ions of the same conductive type as that of the semiconductor substrate 100, that is, the first conductive type(p-type) impurity ions are implanted near the sidewalls of the shallow impurity layer 103 below the gate electrode 102, thus forming a halo ion implantation layer 104. At this time, to implant halo ions into a lower side of the gate electrode 102, an ion implantation is carried out at approximately 25xcx9c30 degree angle from a direction vertical to the surface of the semiconductor substrate 100. At this time, the incidence angle leaned at 25-30 degrees is called an angle of inclination, and indicated as xcex8 in FIG. 1b. 
Generally, in order to form the halo ion implantation layer within the gate electrode 102, impurity ions are implanted at approximately 25-30 degree angle(that is, xcex8=25xcx9c30xc2x0) from a vertical direction of the semiconductor substrate.
Next, as shown in FIG. 1 c, a sidewall spacer 105 formed of an insulating film is formed on the sidewalls of the gate electrode 102. Then, by using the sidewall spacer 105 as a mask, a second conductive type impurity ions are implanted into the semiconductor substrate 100 and heat-treated, thus forming a deep impurity layer 106 with a relatively deep junction depth as compared with the shallow impurity layer 103. The deep impurity layer is called a source/drain of a transistor, and the shallow impurity layer is usually called a Lightly Doped Drain(LDD) in a semiconductor fabrication process.
The halo ion implantation process can be explained in detail as follows. In a conventional DRAM device fabrication process, when drawing a layout of a transistor, the layout is arranged in a vertical or horizontal direction from a flat zone of a wafer.
FIG. 2 illustrates an example of a layout of a conventional semiconductor device. Reference numeral 20 represents a wafer and reference numeral 21 is a flat zone. A region 20a with a high concentration of pattern(gate electrode) such as a cell array region of a DRAM device is illustrated on the left side of the dotted line, and a region 20b with a relatively low concentration of pattern as compared with the cell array such as a peripheral circuit region of a DRAM device is illustrated on the right side of the dotted line. Gate electrodes 22a are concentrated on the region 20a with a high concentration of pattern. Reference numeral 23a shown on both sides of the gate electrode 22a represents an impurity region 23a operating as a source/drain of a transistor. Additionally, gate electrode 22b and impurity regions 23b are illustrated on the region 20b with a relatively low concentration of pattern.
Furthermore, arrow 25 in FIG. 2 indicates an ion implantation direction in which the sources/drains 23a and 23b are exposed to the halo ion implantation when the halo ions are implanted. Bold arrow 24 indicates a halo ion implantation direction in which the halo ions are not implanted into the sources/drains 23a. 
A detailed description thereof is as follows.
As shown in region 20b with a low concentration of pattern in FIG. 2, for a DRAM device, the pattern of the gate electrode 22b in the peripheral circuit region 20b is at once parallel to the flat zone 21 and arranged in a direction orthogonal to the flat zone 21. Therefore, in order to carry out the halo ion implantation near all the sources/drains 23a of the transistor in the peripheral circuit unit, the halo ion implantation is performed in a direction d1 that the flat zone is positioned, and in a direction d2 that the wafer is rotated 90 degrees, 180 degrees, and 270 degrees from the flat zone 21, respectively. Thus, the halo ion implantation is carried out in the cell region 20a as well in four directions d1, d2, d3, and d4. However, as the degree of integration of the DRAM device goes up, the space between the patterns(gate electrodes) becomes very narrow, so that in the case the halo ion implantation is carried out in directions d1 and d3, the halo ions are almost not implanted into the sources/drains 23a. However, in the case that the halo ions are implanted in directions d2 and d4(longitudinal directions of the gate electrode 22a in the cell array region), the sources/drains 23a are directly exposed to the halo ion implantation.
To give more, as shown in FIG. 3a, in the case that the halo ions are implanted in direction 25(that is, directions d1 and d3), the gate electrode 22a serves as an ion implantation mask. But, in the case of direction 24(directions d2 and d4), there is no halo ion cut-off mask, and thus the halo ions are directly implanted into the sources/drains 23a 
Since FIG. 3a is a vertical cross-sectional perspective view along the line IIIbxe2x80x94IIIb of FIG. 2 and FIG. 3b is a vertical cross-sectional view along the line IIIbxe2x80x94IIIb of FIG. 2, the identical drawing symbols in FIGS. 2, 3b, and 3b denote the same component parts, respectively.
However, recently as the degree of integration of the DRAM increases by geometric progression recently, the size of a cell becomes smaller, resulting in a decrease in the capacity of a capacitor. For the above reason, the halo ions implanted into the sources/drains of a DRAM cell transistor cause a reverse effect of worsening the data maintenance characteristics.
That is, since a halo ion implantation layer has a high concentration of impurity, the source/drain junction forms more abrupt junction compared with the case of not applying halo ion implantation process, resulting in stronger electric field concentration at the source/drain junction where the halo ion implantation is implemented. In addition, the DRAM cell is comprised of a transistor and a capacitor, and if the electric field of a source or drain junction connected to a node electrode of the capacitor increases, the data maintenance time shortens, resulting in a decrease in the refresh characteristics. Therefore, to improve the data maintenance characteristics within the DRAM cell, the halo ion implantation process needs to be applied not to the DRAM cell transistor, but to a peripheral circuit or a core circuit alone.
Accordingly, in order to carry out the halo ion implantation into a peripheral circuit and a core circuit alone within the DRAM device and to prevent the halo ion implantation into a cell transistor, the halo ion implantation may be implemented by forming an ion implantation mask on the DRAM cell. However, such a method requires a photolithography process and then, an ion implantation mask removal and cleaning processes thereof, making the halo ion implantation process complicated, increasing the livelihood of a damaged and contaminated semiconductor substrate, and thereby having a poor reliability of the semiconductor substrate.
Accordingly, the present invention is devised to solve the conventional arts problems, and it is an object of the present invention to provide a halo ion implantation method for improving the data maintenance and refresh characteristics of a DRAM device without any extra process steps such as a photolithography process and a cleaning process.
The present invention, in a semiconductor device having a part with a high concentration of gate electrode pattern such as a cell array and a part with a low concentration of gate electrode pattern such as a peripheral circuit, has another object of providing a halo ion implantation method for a semiconductor device for implanting halo ions only into the sources/drains in the part with a low concentration of pattern and not implanting the halo ions into the part with a high concentration of pattern, without any extra mask forming process steps.
To achieve the objects of the present invention, there is provided a halo ion implantation method for a semiconductor device comprising a process for forming a plurality of gate electrodes in a cell array region on a semiconductor substrate so as to be arranged in parallel in one-way and a process for implanting the halo ions within the range of 25xc2x0 to 30xc2x0 vertical angle of inclination at an angle where a wafer is rotated horizontally within the range of 25xc2x0xcx9c65xc2x0 in a clockwise direction or in a counterclockwise direction from a direction orthogonal to a longitudinal direction of the gate electrodes.
To achieve the objects of the present invention, there is provided a halo ion implantation method for a semiconductor, wherein when the gate electrodes of a DRAM cell transistor are arranged in a direction horizontal or vertical to a flat zone, ion implantation is implemented in a direction that a wafer is rotated by xcfx86 (xcfx86 is between 25xc2x0xcx9c65xc2x0) from a direction orthogonal to the flat zone.
Also, to achieve the objects of the present invention, in a semiconductor device having a region with a relatively low concentration of gate electrode and a region with a relatively high concentration of gate electrode, in order to implant the halo ions only into the region with a relatively low concentration of gate electrode, there is provided a halo ion implantation method for a semiconductor device, wherein the halo ion implantation is implemented in a direction of 45xc2x0xc2x120xc2x0 from a direction orthogonal to a longitudinal direction of the gate electrodes in the region with a high concentration of gate electrode.
In addition, to achieve the objects of the present invention, in a semiconductor device having a region with a relatively low concentration of gate electrode and a region with a relatively high concentration of gate electrode, in order to implant the halo ions only into the region with a relatively low concentration of gate electrode, there is provided a halo ion implantation method for a semiconductor device, wherein xcfx86 is a horizontal angle of rotation at which a wafer is rotated in a clockwise direction or in a counterclockwise direction from a direction orthogonal to a longitudinal direction of the gate electrodes formed on the region with a relatively high concentration of gate electrode, xcex8 is a vertical angle of inclination of incident ions from a direction vertical to the surface of the wafer, h is the height of gate electrodes of a large number of transistors forming a cell array of a DRAM device, s is the length of a space between the gate electrodes, and the halo ions are implanted within a range satisfying |tanxcfx86xc3x97cosxcex8| greater than s/h.
Particularly, there is preferably provided a halo ion implantation method for a semiconductor device, wherein (p, a horizontal angle of rotation of the wafer is 45xc2x0, 135xc2x0, 22xc2x0 and 315xc2x0, and xcex8, a vertical angle of inclination is from 25xc2x0 to 30xc2x0.